High-k and metal filled trench-type edram capacitor with electrode depth and dimension control

ABSTRACT

Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.

FIELD OF THE INVENTION

The present invention generally relates to storage capacitor structuresfor memory cells in semiconductor integrated circuits formed at highintegration density and, more particularly, to high-K material and metalfilled eDRAM capacitors formed at extremely high integration density andthe increase of process windows and overlay tolerance during manufactureof such devices.

BACKGROUND OF THE INVENTION

Needs for increased functionality, capacity and performance ofintegrated circuits of a given chip size and increased economy ofmanufacture have driven the size of electronic elements thereof toextremely small sizes and extremely high integration densities. Smallsize of active and passive electrical components allows increasedintegration density and increased numbers of electrical devices on achip of given area for increased functionality. High integration densityallows interconnections to be of reduced length which supports higherclock rates of operation while reducing susceptibility to noise.However, such small sizes and high numbers of electronic elements hasgreatly increased the accuracy with which such elements must be formed.For example, it is known that tools such as process chambers forintegrated circuit manufacture are not precisely uniform over the entireprocessing area of a wafer and allow small variations in the rate atwhich various processes such as etching are performed across the area ofa semiconductor wafer from which many concurrently formed chips arelater diced. Further, deposition and etching processes are known to beaffected by chip design since differing densities of elements and areasfor deposition and etching can locally concentrate and/or depleteetchant or material precursor concentrations. Both of these effects arebecoming significant at current and foreseeable integration densitiesand electronic element sizes. At the present state of the lithographicart for semiconductor manufacture, variations in structures due to suchnon-uniformity of the progress of material deposition and removalprocesses can cause defects of sufficient severity to significantlyreduce manufacturing yield.

While all types of semiconductor devices are potentially subject to suchproblems, high density memory arrays and processors having embeddedmemory arrays are particularly subject to the occurrence of such defectsand consequent loss of manufacturing yield. This susceptibility to lossof manufacturing yield is principally due to the need for maximumpossible memory capacity requiring extremely high density of capacitorsformed at or near the limits of lithographic resolution which alsocontributes to lack of process uniformity across the chip and waferareas. Deep trench storage capacitors which include a dielectricmaterial having a particularly high dielectric constant to increasecapacitance and which are metal filled for high write, erase, sense andrefresh speeds have been found to be particularly susceptible to suchdefects and compromise of manufacturing yield. It has also been recentlyobserved that such storage capacitor structures are particularlysensitive to overlay errors, especially when forming connections betweenelectrodes when the deep trench capacitors are optimally nested forextreme integration density.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a methodand structure for improving uniformity of material removal processesduring manufacture of semiconductor integrated circuits.

It is another object of the present invention to provide for uniformityof material removal processes using a structure and method thatincreases overlay error tolerance.

In order to accomplish these and other objects of the invention, amethod of semiconductor device manufacture is provided comprising stepsof forming an aperture in a layer of material extending over othermaterial, applying an organic planarizing layer (OPL) over a surface ofthe integrated circuit and within the apertures, partially removing theOPL within the apertures to form OPL plugs in the apertures, performingmaterial removal steps around the apertures or OPL plugs, removing theOPL plugs, and performing additional processes on the electronicelement.

In accordance with another aspect of the invention, a method ofsemiconductor device manufacture is provided comprising steps of formingan aperture in a layer of material extending over other material,applying an organic planarizing layer (OPL) over a surface of theintegrated circuit and within the apertures, partially removing the OPLwithin the apertures, removing the OPL material within the apertures,the step of removing OPL material including lateral etching of OPLmaterial and other exposed material in the aperture, and performingadditional processes on the electronic element.

In accordance with a further aspect of the invention, a semiconductorwafer is provided including an electronic element formed below a surfaceof a substrate or layer of semiconductor material, and a conductive bodyof material formed within an aperture and in contact with the electronicelement wherein the conductive body of material is recessedsubstantially uniformly at all locations on the semiconductor wafer.

In accordance with yet another aspect of the invention, a semiconductordevice is provided including two electronic elements formed below asurface of a substrate or layer of semiconductor material, twoconductive bodies of material formed within respective apertures and incontact with respective ones of the two electronic elements, and a strapconnection connecting the two conductive bodies wherein a width of thestrap connection corresponds to a degree of overlay error in thelocation of the strap connection relative to the two conductive bodies.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIGS. 1, 2, 3, 4, 5 and 6 are cross-sectional views illustrating basicsteps in the formation of deep trench (DT) Hi-K and metal filledcapacitors for which the invention is particularly well-suited,

FIGS. 7, 8A, 8B, 9A, 9B, 10A and 10B are cross-sectional viewsillustrating the problem of lack of etch uniformity addressed by theinvention,

FIGS. 11, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A and 16B arecross-sectional views illustrating manufacture of a DT capacitor inaccordance with the invention,

FIG. 17 comprises scanning electron microscope images of cross-sectionof DT capacitors illustrating the effectiveness of the invention tosolve problems caused by etching non-uniformity,

FIGS. 18A and 18B illustrate, in plan view, an exemplary misalignmentoverlay error as well as indicating the locations of cross-sectionalview shown in other Figures,

FIGS. 18C and 18D are isometric views showing a comparison of goodalignment and misalignment of FIGS. 18A and 18B, respectively,

FIGS. 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A and 23B arecross-sectional views of DT capacitors illustrating an exemplary problemcaused by the overlay error misalignment illustrated in FIG. 18B,

FIGS. 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, 28B, 29A and 29B arecross-sectional views illustrating avoidance of the exemplary problem ofoverlay error misalignment and the increase of overlay error tolerancein accordance with the invention, and

FIGS. 30A, 30B and 30C are scanning electron microscope imagesillustrating the effectiveness of the invention to engender overlayerror tolerance.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

Referring now to the drawings, and more particularly to FIG. 1, there isshown, in cross-section, an initial stage in manufacture of deep trench(DT), Hi-K and metal filled capacitors. It should be understood that themanufacturing stages illustrated are generalized and arranged to conveya basic understanding of the manufacturing process which gives rise tothe problems addressed by the invention and the invention is notdepicted therein, no portion of any of FIGS. 1-6 is admitted to be priorart in regard to the present invention. These Figures will therefore bedesignated “Related Art”. By the same token, while manufacturingprocesses will be explained in regard to use of asemiconductor-on-insulator (SOI) substrate or wafer having a siliconactive layer, as is preferred, the invention may be successfullypracticed to obtain its meritorious effects which any substrate or waferof any structure and having an active layer and handling substrate ofany semiconductor material and an insulator layer of any electricallyinsulating material on which a high quality semiconductor active layercan be developed. The cross-sections shown in FIGS. 1-6 are taken alongdashed line I-I of the plan view illustrated in FIG. 18A.

As illustrated in FIG. 1, the preferred SOI wafer comprises a handlingsubstrate 10, so-called since it principally provides mechanicalrobustness to the wafer and the thin insulator layer 12 (sometimesreferred to as a buried oxide or BOX layer, regardless of actualcomposition) and thin semiconductor layer 14 formed thereon, but alsoprovides a conductive common electrode for an array of deep-trench (DT)capacitors to be formed therein. At the stage of capacitor productionillustrated in FIG. 1, a thin pad oxide layer 16 and pad nitride layer18 have been formed over the active semiconductor (e.g. silicon) layer14. The combination of pad oxide 16 and pad nitride 18 can be etchedselectively to each other and, when patterned (e.g. using a resistlayer, not shown) that can be selectively exposed to energy whichdevelops differential solubility to form a pattern), provide a hard maskfor etching of the semiconductor layer 14, the insulator later 12 andthe handling substrate 10. This etching process should be substantiallyanisotropic (for which many suitable processes are known) to formopenings 20 without significant etching of the ends of layers 12 and 14as they are exposed and should extend only slightly into the handlingsubstrate 10 so that a DT spacer 22 formed of any material that willwithstand the further etching of the handling substrate 10 will fullycover the ends of the semiconductor and insulator layers 12, 14 exposedwithin the trench as illustrated in FIG. 2.

Then, as shown in FIG. 3, deep trenches 24 are etched, preferably usinga substantially anisotropic etching process For which many suitableprocesses are well-known. To further increase the area of the interiorof the deep trenches, an isotropic etch, for which many suitableprocesses are known, is then performed within the deep trenches, asshown at 24′ of FIG. 4. The process of enlarging the deep trenches insuch a manner is referred to as bottling since it forms a bottle-likeshape that is larger in diameter than at opening 20. Then, as shown inFIG. 5, the enlarged deep trenches 24′ are lined with an isotropicallydeposited Hi-K dielectric layer 26 and a conductive metal or metalnitride layer 28. The remainder of the deep trench 24′ is then filledwith conductive polysilicon 30 which is then recessed (including theupper edges of the Hi-K material 26 and conductive metal nitride 28liners) to a point within the thickness of insulator layer 12, referredto hereinafter as recess 1. Then, to make a connection to the metal ormetal nitride liner 28 and polysilicon fill 30, additional dopedpolysilicon 34 is deposited and recessed (36) to a point within theactive semiconductor layer 14, referred to hereinafter as recess 2. Thedoped polysilicon improves conductivity of the contact but principallyserves to protect the upper edges of the metal or metal nitride layerand Hi-K layer from oxidation or attack from other chemical processes.The thickness of additional doped polysilicon also serves to reducecriticality of etch rates of additional etching processes that will beperformed later but a thickness to fully protect against defects fromsuch a variation in etch rates cannot, as a practical matter, beprovided. This above-described process substantially completes the DTcapacitor structure, which is often referred to as a storage node,although significant additional processing will be required to formconnections to doped polysilicon contacts 34.

Referring now to FIGS. 7-10B, a problem that arises from non-uniformityof etching during such additional processing, referred to as activelayer lithography in which portions of active semiconductor layer 14 areselectively removed prior to connection formation but to which asolution is provided by the invention will now be explained. As alludedto above, all reaction vessels for performing semiconductor processingwill exhibit some degree of non-uniformity of the rate at which materialdeposition or removal will occur due to slight variations intemperature, material flow rate and the like. A similar effect is alsoobserved due to differences in the ratio of the area on which materialis selectively deposited or the area from which it is being removed tothe area of a portion of the wafer surface that causes local variationof the concentration of reactants near the surface where deposition oretching is being performed. For example, if a large fraction of aparticular area is being etched, there will be a higher percentage ofetched material and a reduced concentration of etchant near the wafersurface as reaction products of the etching process than if a smallerfraction of a similar area is being etched. Therefore, etching willproceed more rapidly in areas where the change in concentration ofreaction products is smaller. Since many etching processes cannot becontrolled by using layers of selectively etchable material as an etchstop for the process such processes are performed as timed etches wherean etch rate is assumed from empirical data. The time required to removea particular amount or thickness of material can then be computed.However, since the entirety of the thickness of a layer of material mustgenerally be removed, the required time must be computed in regard tothe lowest anticipated etch rate for any area on the wafer and, as aconsequence, any variation in etch rate will be a more rapid etch rateas is assumed in the illustrations of FIGS. 8A-10B; the Figuresdesignated as “A” illustrating the results of a timed etch assuming thelowest anticipated etch rate as nominal and the Figures designated “B”illustrating the results of an etch process for the same length of timebut which proceeds at a rate which is above the lowest anticipated ornominal etch rate. Again, these Figures are generalized and arranged toconvey an understanding of the problems addressed by the invention andno portion of any of FIGS. 7-10B is admitted to be prior art in regardto the present invention. As above, since the invention is notillustrated in these Figures, they have been designated as “RelatedArt”.

FIG. 7 shows essentially the same structure as shown in FIG. 6 producedby the generalized method discussed above. However, an organicplanarizing layer (OPL) 40 has been applied, followed by a resist layer42 which has been patterned. Numerous OPL materials are known which aresuitable for the practice of the invention. OPL materials can be etchedselectively to most other materials of interest for manufacture ofsemiconductor devices and, since they are similar in composition andoptical properties to photo resists, can be removed easily. It should benoted that the OPL layer 40 fills recess 2 (36) and produces a planartop surface that facilitates exposure of resist 42 which will have asimilarly planar surface. FIGS. 8A and 8B show the result of etching OPLlayer 40 in accordance with the pattern/opening in resist layer 42 toform opening(s) 44. This etching process is timed to completely removethe OPL material in opening 44 to the surface of the pad nitride 18 andthe surface of the doped polysilicon fill 34 as shown at 46 of FIG. 8A.However, where the etch proceeds more rapidly, the etching processattacks the polysilicon fill 34 and removes some of that material belowthe surface of recess 2 as shown at 48 of FIG. 8B.

To eventually form a strap connection between the doped polysiliconregions as is generally desirable in capacitor memories of this type theremaining pad oxide layer 16 and the semiconductor layer 14 remainingfrom the etch of FIG. 2, discussed above, must also be similarly removedusing selective etching. As shown in FIGS. 9A and 10A, these etchingprocesses will necessarily also attack the doped polysilicon fill 34 asshown, for example, at 46′ of FIG. 9A. However, it will be recalled fromthe foregoing that the actual etch rate will have contributions fromboth non-uniformities of operation of the reaction vessel and the layoutof the integrated circuit design, itself. Therefore, the regions thatexhibit an increased etch rate will be the same as for the pad nitridelayer etch described above although the relative increase of etch ratemay differ somewhat. Therefore there will be additional excess etchingof the polysilicon fill 34 during both the oxide and active siliconlayer etching processes as shown at 48′ in FIGS. 9B and 10B. As shown at48′ of FIG. 10B the excess etching reaches and further recesses aportion of the first polysilicon fill 30 (e.g. beyond the surfacecreated by the first recess) and exposes the edge of the metal or metalnitride and Hi-K material layers 28 and 26, leading to the possibilityof corrosion or other damage that is undesirable for semiconductormanufacturing. That is, further etching can occur since strong acidssuch as hydrofluoric acid or sulfuric acid may be present and can alsocause oxidation. Oxidized metal or metal nitride is also of increasedvolume and can cause warping or cracking of the chip as well aspreventing the metal or metal nitride from functioning as an electrodeof the capacitor. Properties of the Hi-K material can also besignificantly modified and compromised by only slight contamination withoxides or silicates causing reduction in capacitance and increase inleakage. Increased alignment error in later process steps withsubsequent thermal processing caused by the oxidized metal or metalnitride can limit manufacturing yield or completely prevent furtherprocessing from being properly performed, resulting in complete loss ofa wafer. Any such defect is necessarily adequately severe as to causechip malfunction or at least a significant reduction in operatingmargins and has the potential for reducing manufacturing yield.

To avoid such a problem or other problems due to non-uniformity ofmaterial removal processes, the invention will now be explained withreference to FIGS. 11-16B. FIG. 11 is substantially identical to FIG. 7with the OPL layer 40 and the patterned resist layer 42 in place on thestructure developed in the process discussed above in connection withFIGS. 1-6, but is repeated here for purposes of continuity of thedescription of the invention. As shown in FIGS. 12A and 12B, the OPLlayer is etched in accordance with the aperture/patterning of resistlayer 42. However, in this case, in accordance with the invention, thisetch of the OPL layer is a timed etch that is terminated above the dopedpolysilicon 34, leaving a plug 110 of OPL material above it. As shown inFIG. 12B, where the etch proceeds more rapidly, less OPL materialremains, as shown at 120 of FIG. 12B but even the reduced thickness iseffective to function as a plug. The pad nitride and pad oxide layeretches can then be performed as shown in FIGS. 13A and 13B which arerelatively selective to the OPL although slight etching of the OPLmaterial occurs and the OPL plug remains in place as shown at 110′ ofFIGS. 13A and 120′ of FIG. 13B. Use of a combination of CHF₃ and CF₄ gasprovides ample selectivity to carry out this etching processsuccessfully and with substantial windows of process parameters suchthat the OPL plug remains intact even where an increased etch rateoccurs. The pad oxide etch can then be similarly performed. It shouldalso be noted that the OPL material in the opening as the OPL plugprotects the polysilicon during the pad nitride and pad oxide etchalthough some etching of the OPL plug occurs. As a result, there is nopolysilicon etch during this process and any non-uniformity of etchingis effectively absorbed by the OPL plug which is later removed anduniformity of the location of the upper surface of the polysilicon 34 isgreatly improved. The OPL plug can be removed prior to the activesemiconductor layer etch as shown in FIGS. 14A and 14B. Sufficientselectivity between silicon (including the doped polysilicon fill 34,and OPL etching can be obtained using HBR, O₂ and CO₂ gas with CO₂ gasbeing a key component for high selectivity. As a result, thenon-uniformity of OPL plug thickness does not transfer to etching of thepolysilicon.

Then, as shown in FIGS. 15A and 15B the active silicon layer 14 and theDT recessed polysilicon are simultaneously etched. This process step inwhich silicon and polysilicon are etched together, is the only processthat affects polysilicon depth non-uniformity. This results in a recessof a portion of the doped polysilicon with better depth uniformitywithin the wafer as is desirable to form consistent strap connectionsacross the wafer and with better quality Hi-K material and metal ormetal nitride material. The resist and remainder of the OPL material canthen be removed as illustrated in FIGS. 16A and 16B. It should be notedthat the structures resulting in the OPL plug removal and all followingsteps are substantially identical regardless of differences in etchrates and that a substantial thickness of doped polysilicon remainsabove the metal or metal nitride electrode and Hi-K material whichremains reliably protected throughout the process in accordance with theinvention. This protection is particularly evident in the scanningelectron microscope images corresponding to FIGS. 10B and 16A and B inFIG. 17.

Referring now to FIGS. 18A-18B, a plan view of respective portions of amemory array is schematically illustrated. In FIG. 18A, DT capacitorsare depicted in connection with the active layer which is a part of thestrap connectors as described above properly aligned therewith. In FIG.18B, the active layer and, hence, the strap connectors are misaligned byan overlay error shifting the connectors in the Y-direction. Thismisalignment, as illustrated, is sufficient to additionally overlie andconnect with DT capacitor contacts of other storage nodes; effectivelyshorting the strap connectors to each other through the DT capacitorcontacts and rendering the array inoperable. This undesirable connectioncan be more readily visualized from the isometric depictions of properalignment and y-direction misalignment illustrated in FIGS. 18C and 18D,respectively. The structures which cause this defect will now bediscussed in regard to FIGS. 19A-23B and the solution provided by theinvention will be discussed in connection with FIGS. 24A-29B. As before,Figures having an “A” designation are cross-sections taken at sectionline II-II of FIG. 18A and have strap connections which are properlyaligned while Figures having a “B” designation are cross-sections takenat section line III-III if FIG. 18B and illustrate results of overlayerror misalignment. It should be noted that section lines II-II andIII-III are orthogonal to section line I-I. Essentially, the OPL plugtechnique described above can be tuned to provide substantial overlayerror tolerance.

FIGS. 19A and 19B correspond to the structure shown in FIG. 7 or FIG.11. However, the location of the patterned SOI, pad oxide, pad nitrideand resist 130 and 130′ do not correspond to these Figures since thesection shown is different. That is, the sections shown in FIGS. 7 and11 correspond to section line I-I of FIG. 18A while the section shown inFIGS. 19A and 19B correspond to section lines II-II in FIG. 18A andIII-III in FIG. 18B, respectively. It should be noted that the strapconnection connects storage node capacitors which are in front and backof the plane of the page and should not connect to either of thecapacitors illustrated as may be best visualized From FIGS. 18C and 18D.Also, while a portion of the SOI layer was removed in the processdescribed above, the portion shown in FIGS. 19A and 19B will be allowedto remain since it is a portion of the access transistor from the nextrow of DRAM cells and is evident from section line II-II of FIG. 18A.

FIGS. 19A and 19B are identical to each other but for the location ofresist 130′ in FIG. 19B which is misaligned by overlay error such that aportion of the resist 130′ overlies a portion of the doped polysiliconfill contact 34 whereas resist 130 is illustrated in the correctposition between and not overlapping either of storage nodesillustrated. When the OPL material etch is performed, a portion of theOPL material remains above the doped polysilicon fill 34 as shown inFIG. 20B whereas no OPL remains in that area when the resist is properlyaligned as shown in FIG. 20A. Subsequently, when the pad nitride isetched as shown in FIGS. 21A and 21B, this portion of the OPL materialremains. Then, when the SOI and doped polysilicon 34 is etched, theremaining OPL material acts as a mask to prevent etching of a portion ofthe doped polysilicon fill 34; leaving a connection to the remainingportion of the SOI layer that forms part of the access transistor andresulting in a parasitic connection between the storage node and theaccess transistor of the next row, as shown in FIGS. 22B and 23B,rendering the memory inoperable, whereas no such connection remains inthe properly aligned structure of FIGS. 22A and 23A.

Referring now to FIGS. 24A and 24B which are identical to FIGS. 19A and19B (but which are repeated for continuity of description of theinvention, the cases of properly aligned resist 130 and misalignedresist 130′ are again illustrated. As discussed above in connection withFIGS. 12A and 12B, when the OPL material is etched, a timed etch ofreduced duration is performed allowing a plug of OPL material to remainover the entire surface of doped polysilicon fill 34 as shown at 160 ofFIGS. 25A and 25B. In FIG. 25B, due to resist misalignment a portion ofthe OPL material remains above doped polysilicon fill 34 and a portionof the OPL plug. Thereafter, when the pad nitride is etched, OPLmaterial remains at location 140′ while the pad nitride is recessed fromthe OPL plug elsewhere as shown, for example, at 180 of FIG. 26A. Then,when the OPL plugs are removed, the doped polysilicon fill 34 iscompletely exposed due to lateral etching of the OPL that remained dueto the resist misalignment. It is important to note in this regard thatthat OPL plug removal in FIG. 16B illustrated material removal only inthe vertical direction as would occur with an anisotropic etch althoughthe material removal is preferably performed as an isotropic etch. Thus,as shown in FIG. 27B, a lateral component of the OPL plug is removed bylateral etching in a well-controlled manner. Excessive OPL plug lateraletching can reduce the strap region as shown in FIG. 30C or beyond. Thelateral component of OPL plug etching can be changing gas pressure andother conditions, particularly reducing Hbr concentration and increasingoxygen gas flow rate. The amount of the lateral material removal can bebased on the balance or trade-off between alignment error and strapresistance increase. That is, when overlay or alignment error is asignificant factor in loss of manufacturing yield, lateral etch can bemore aggressive, even though desirably low strap resistance may becompromised. Therefore, the doped polysilicon fill 34 can be recessedproperly in the normal manner to a point below the remaining SOI and noshorting of the DT capacitor thereto can occur, regardless ofmisalignment of resist 130′, as shown at FIGS. 28A, 28B, 29A and 29B. Inthis regard, it should be noted that the remaining SOI is protected bythe pad nitride and no dimensional change occurs.

The efficacy of the invention to provide both an avoidance of defectsdue to non-uniformity of etching rates and to provide an increasedtolerance for overlay misalignment errors when connections are made canbe readily appreciated from the SEM images shown in FIGS. 30A-30C. FIG.30A may be regarded as showing the strap connections as would be formedby a conventional process or in accordance with the invention where nomisalignment was presented. That is, even in accordance with theinvention, no lateral component of OPL etching is present or requiredand adequate spacing A′ and strap connection width A are substantiallyequal and adequate when overlay accuracy is good. FIGS. 30B and 30C,however, may be regarded as cases where misalignment is present todifferent degrees (misalignment in FIG. 30C being larger where moreaggressive lateral OPL etching is performed) even though misalignment isnot evident in these images. Lateral etching can be performed regardlessof whether or not misalignment is present but would ordinarily not beperformed unless needed. In this regard, lateral etching may beselectively performed based on whether or not resting at the wafer levelshows that it is necessary or desirable. Thus FIG. 30B shows a reductionin strap connection width B′ and increased clearance (B−B′/2) betweenthe active layer and the next tow storage node in the case ofmisalignment. The amount of clearance can remove the parasiticconnection shown in FIG. 18D. The process without a lateral etchcomponent, resulting in the structure of FIG. 30A cannot remove theparasitic connection without strap width reduction and will cause thememory cell (and others to which a connection is mad) to becomeinoperable. FIG. 30C, depicting more aggressive lateral etchingillustrates a further decreased strap connection width C′ and furtherincreased clearance C (e.g. C−C′/2). In summary, in all of theseFigures, the pattern inside of the circles is defined by the OPLmaterial. In the case of lateral OPL plug removal (e.g. wheremisalignment has occurred), the patterns are made smaller by an amountcorresponding to the lateral OPL removal.

In view of the foregoing, it is clearly seen that the invention, by thesimple expedient of leaving OPL material plugs in place in aperturesthrough partial OPL material etching and removal of the OPL materialplugs after other etching processes has been performed that reducesprocess variations and protects against the underlayer of metal or metalnitride from being exposed, thus improving manufacturing yield.Increased process parameter windows and increased tolerance of overlayerror are also provided by a simple, and non-critical process that doesnot significantly increase process complexity or cost.

While the invention has been described in terms of a single preferredembodiment, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

1-17. (canceled)
 18. A semiconductor wafer including an electronicelement formed below a surface of a substrate or layer of semiconductormaterial, and a conductive body of material formed within an apertureand in contact with said electronic element wherein said conductive bodyof material is recessed substantially uniformly at all locations on saidsemiconductor wafer.
 19. The semiconductor wafer as recited in claim 18wherein said electronic element is a deep trench capacitor.
 20. Asemiconductor device including two electronic elements formed below asurface of a substrate or layer of semiconductor material, twoconductive bodies of material formed within respective apertures and incontact with respective ones of said two electronic elements, and astrap connection connecting said two conductive bodies wherein a widthof said strap connection corresponds to a degree of overlay error in thelocation of said strap connection relative to said two conductivebodies.
 21. The semiconductor device as recited in claim 20 wherein saidconductive bodies of material are recessed substantially uniformly atall locations of said semiconductor device.
 22. The semiconductor deviceas recited in claim 21 wherein one of said electronic elements is a deeptrench capacitor.